Atrisa
AI agents that turn plain-language descriptions into analog circuit designs and simulations.
On the record
Checkpoint: Outcome of Astrus's targeted first paid Tier-1 semiconductor pilot
The call
Atrisa is a pre-revenue YC startup chasing a niche that Cadence and Synopsys are already automating inside their own tools, while a better-funded rival courts the same Tier-1 customers first.
Atrisa is trying to sell AI software that helps engineers design analog circuits faster. The problem is that Synopsys and Cadence, the two companies that already dominate chip design software, have already launched their own AI tools and have no reason to buy or partner with Atrisa instead. Atrisa has a small dataset of 2,000 circuits, no customers locked into its workflow yet, and is racing against a better-funded startup called Astrus that started months earlier. The one thing that could change everything: if Astrus fails to land a real paying customer at a major chip company by mid-2026, it might prove there is still room for smaller players like Atrisa to compete; if Astrus succeeds, the window closes fast.
Why
01
AI pressure: Cadence ChipStack (OpenAI Codex + NVIDIA Nemotron) and Synopsys ASO.ai. Both EDA giants already run agentic analog AI inside their own platforms, the exact capability Atrisa is trying to sell separately. Could AI do the core job? Yes, likely.
02
Bigger players: Synopsys and Cadence Design Systems. They hold roughly 75% of the EDA market and can fold agentic analog tools into existing seat licenses at no extra sales cost. Could a giant copy it? Yes, easily.
03
What protects it. A roughly 2,000-circuit proprietary dataset built in-house, though it is small, unbenchmarked, and not yet proven to beat incumbent tools.
What would change this call
Whether Astrus announces a paid Tier-1 semiconductor pilot before Q2 2026. Would show Astrus, not Atrisa, is winning the analog-AI startup race for enterprise customers.
Whether Atrisa announces its own paid pilot with a large semiconductor company within 6-12 months. Would show Atrisa can convert its dataset into real enterprise traction before the window closes.
Whether Cadence or Synopsys extend their Computex 2026 agentic analog tools into production-scale offerings. Would show incumbents absorbing the capability Atrisa is betting on, narrowing its opening.
Whether Atrisa announces its own paid pilot with a large semiconductor company within 6-12 months. Would show Atrisa can convert its dataset into real enterprise traction before the window closes.
Whether Cadence or Synopsys extend their Computex 2026 agentic analog tools into production-scale offerings. Would show incumbents absorbing the capability Atrisa is betting on, narrowing its opening.
Key numbers
- Synopsys and Cadence hold ~75% of global EDA market
- Direct rival Astrus raised $8M seed funding
- Atrisa's proprietary dataset covers ~2,000 circuits
Named risks
- No disclosed paid pilots or revenue as of June 2026 despite 12-18 month market window.
- Incumbents Synopsys and Cadence face no business-model conflict absorbing agentic analog AI into existing seats.
- Better-funded rival Astrus has 6-12 month head start on Tier-1 semiconductor conversations.
- 2,000-circuit dataset is small relative to incumbents' decades of proprietary customer design data.
- YC-only funding with no disclosed follow-on seed/Series A as of July 2026.
Rivals, as read in July 2026
| Rival | Direction | Evidence |
|---|---|---|
| Astrus | gaining on | Raised $8M seed and began Tier-1 pilot talks by Aug 28 2025, 6-12 months ahead of Atrisa |
| Cadence Design Systems | losing to | Shipped Level-5 ChipStack agentic tool with Codex+Nemotron by Jun 11 2026, no cannibalization barrier |
| Synopsys | losing to | Vendor-claimed 25-100x analog productivity gains from ASO.ai/Custom Compiler as of Jul 7 2025 |
| Silimate | contesting | Adjacent digital RTL copilot reportedly licensed by Fortune 500 firms and chip unicorns by Mar 11 2026 |
Questions people ask
- Is Atrisa profitable in 2026?
- No. As of June 12, 2026, Atrisa is pre-revenue with no disclosed ARR or paying enterprise customers. Its stated near-term goal is simply to secure a paid pilot with a larger semiconductor company, per swethasrinivasan.substack.com, meaning it has not yet converted its product into revenue.
- Could incumbents like Synopsys or Cadence replace what Atrisa builds?
- Yes, largely. Cadence shipped 'Level-5 autonomy' ChipStack agents at Computex 2026 (June 11, 2026) using OpenAI Codex and NVIDIA Nemotron, and Synopsys markets ASO.ai claiming 25-100x gains (vendor-claimed, July 7, 2025), both inside tools they already sell with no cannibalization conflict.
- Who is Atrisa's biggest competitor?
- Astrus, a Toronto/Kitchener-Waterloo startup that raised $8M USD ($11M CAD) in seed funding on August 28, 2025, and was already in Tier-1 semiconductor talks targeting paid pilots for early 2026, roughly 6-12 months ahead of Atrisa.
- Who owns Atrisa?
- Atrisa is a private, Y Combinator-backed startup (W26 batch) with no independent VC round disclosed as of July 2026. Co-founders are CEO Sayan Mitra (ex-KLA Semiconductors), CTO Atman Kar (ex-Texas Instruments), and COO Rithik Jain, per ycombinator.com.
- What is Atrisa's competitive moat?
- A proprietary dataset of roughly 2,000 analog circuits built in-house, cited June 12, 2026 by swethasrinivasan.substack.com, because public analog training data is scarce. It's real but tiny next to Synopsys and Cadence's decades of customer design data.
- Has Atrisa raised money beyond Y Combinator?
- No public seed or Series A round beyond YC funding was found as of a July 9, 2026 PitchBook profile check; the company is tracked as funded but no valuation or external lead investor has surfaced publicly.
Timeline
- 2026-06-12Substack profile reveals Atrisa's ~2,000-circuit dataset and pre-pilot, pre-revenue status
- 2026-06-11Cadence and Synopsys demo agentic analog/EDA tools at Computex 2026 GTC Taipei
- 2026-06-02Atrisa publicly launches on YC, rebranding from Refortifai
- 2026-05-20Report cites Synopsys and Cadence at roughly 75% combined EDA market share
- 2026-03-24YC W26 batch breakdown published, situating Atrisa among 199 companies
- 2026-03-11Silimate (adjacent digital chip-design AI) reported licensed by Fortune 500 firms
- 2025-08-28Rival Astrus raises $8M USD ($11M CAD) seed, targets Tier-1 pilots for early 2026
- 2025-07-07Synopsys claims 25-100x productivity gains from AI analog design tools (vendor-claimed)
Revision history
27 July 2026
First assessed. Losing its protection. The text above is fixed as of this date and is not edited afterwards.
In the same band
Sources
- AI-Powered Analog Design Solutions for AIMC Innovation (2025-07-07)
- Cadence and Synopsys Accelerate the Agentic EDA Race (2026-06-11)
- Cadence Design Systems Competitors: CDNS vs SNPS, INTC 2026 (2026-05-20)
- Launch YC: Atrisa: Agents for Analog Circuit Design (2026-06-02)
- Atrisa and the Case for Agentic Analog Design (2026-06-12)
- Atrisa (formerly Refortifai): AI Agents for Analog Circuit Design
- Astrus announces $11 million CAD to automate semiconductor design with AI (2025-08-28)
- Silimate CEO pioneers AI debugger for chip designers (2026-03-11)
- laiyao1/AnalogCoder
- Agentic LLM-based Workflow for Reasoning-Driven Explainable and Sample-Efficient Analog Circuit Sizing (2025-06-29)
- Atrisa 2026 Company Profile: Valuation, Funding & Investors
- YC W26 Batch Breakdown: Deep Dive on 199 Companies With Founder Data (2026-03-24)